The present invention relates generally to semiconductor devices, and more particularly, to a structure and method for reducing substrate bowing resulting from the formation of strained SiGe layers having a high percentage of germanium on silicon substrates.
In field effect transistor (FET) devices, the introduction of stress (i.e., compressive or tensile) to the channel region through high concentrations of germanium may be used in order to improve carrier mobility, which may subsequently increase device performance. The bandstructure of SiGe becomes more germanium-like as the concentration of germanium reaches 85% and above. Because of the increased carrier mobility at these bandstructures, 85% SiGe to pure germanium is a potential candidate to be used in the channels of devices having a 7 nm or lower node.
To work with current complementary metal oxide semiconductor (CMOS) technology, these high percentage SiGe or pure germanium layers may be formed on a silicon substrate. However, forming 85%-99% SiGe or pure germanium on silicon is very challenging due to the high lattice mismatch of 3.6% or more. The lattice mismatch between the SiGe and the silicon may cause defects in the SiGe layer such as dislocations and stacking faults. Typically, the SiGe layers may be grown very thick (5-10 microns or more) and may be graded in order to trap most of the defects at the interface. The defect-free upper portion of the SiGe layer may then be smart cut wafer bonded onto a silicon handle wafer to form a silicon germanium on insulator (SGOI) wafer.